1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to an improved method for manufacturing integrated circuit devices including bipolar transistors by the master slice method.
2. Description of the Prior Art
The master slice method, which is one of the methods for manufacturing LSI or like semiconductor devices, is a method which employs a common master pattern in the manufacturing process, from a starting step to a diffusion one, to form transistors, resistors and other elements in a substrate and wherein the circuit elements are wired in a particular pattern selected in accordance with a semiconductor device desired ultimately to be obtained. With such a master slice method, in the case of producing LSI's, especially in the case of manufacturing many kinds of LSI's in small quantities of each kind, the manufacturing costs and times can be reduced since one part of the manufacturing process is common to all of them.
Generally, in the formation of circuits, it is often required to provide a predetermined current ratio between a plurality of semiconductor elements.
For obtaining a predetermined current ratio through utilization of semiconductor elements of the same characteristics to meet such a requirement, it is considered possible to connect resistors r1 and r2 of different values to transistors Tra1a And Tra1b respectively, as shown in FIG. 1. Letting the currents flowing in the transistors Tra1a and Tra1b be represented by I1 and I2, respectively, there exists a relationship, I1/r2.apprxeq.I2/r1.
In the case where the predetermined current ratio is intended to be obtained by changing the currents flowing in the transistors Tra1a and Tra1b of the same characteristics by using the resistors, as described above, however, the emitter current density of each transistor varies, so that the transistor Tra1a or Tra1b operates at a point different from its normal operating point and the temperature dependency of their respective base-to-emitter voltages VBE differ from each other, resulting in the preset current ratio varying with temperature.
A remedy for such a defect is to employ transistors of different emitter areas. Assuming that transistors Tr1, Tr2, Tr3, Tr4, . . . shown in FIG. 2 have different emitter areas S1, S2, S3, S4, . . . , respectively, it follows that I1/S1=I2/S2. In such a case, it is possible to provide a required current ratio between adjacent ones of the transistors and to retain the emitter current density of each transistor constant; accordingly, the transistors operate in their normal mode of operation and do not suffer characteristic variations due to temperature.
Now, a description will be given of the method for manufacturing an integrated circuit device including such transistors of different emitter areas according to the master slice method. For facilitating a better understanding of the description, the following will describe the case in which three kinds of LSI's (semiconductor devices), each formed by 10 transistors of one of three kinds of bipolar transistors Tr1, Tr2 and Tr3 whose emitter areas are in the ratio of 1 to 2 to 3, are manufactured by the master slice method. With their emitter areas selected in the ratio of 1 to 2 to 3, the bipolar transistors exhibit different characteristics, for example, in that their collector voltage ratio relative to the same base-emitter voltage V.sub.BE is 1 to 2 to 3.
With the master slice method, the same master pattern is used for a plurality of different kinds of LSI's, but in the case of this example, it is necessary to prepare a master pattern including 10 transistors of each of the three kinds of bipolar transistors Tr1, Tr2 and Tr3. FIG. 3 shows a pattern of each of the three kinds of bipolar transistors Tr1, Tr2 and Tr3. In FIG. 3, the hatched parts are their emitter regions 11 and the areas of the emitter regions of the bipolar transistors Tr1, Tr2 and Tr3 are selected in the ratio of 1 to 2 to 3. The respective reference numerals 12 indicate base regions; 13 designate collector regions; 14 identify collector contact regions; 11', 12' and 13' denote contact holes, or windows for the respective regions; and 15 represents an isolation region for isolating each of the transistors from the others. FIGS. 4A to 4C are explanatory of this example, schematically illustrating master patterns. In FIGS. 4(A), (B) and (C), each part indicated by reference numeral 16 is a region in which are prepared ten (10) of each of the three kinds of bipolar transistors Tr1, Tr2 and Tr3. Each part indicated by reference numeral 17 is a region prepared and reserved for elements which perform other functions than those of the bipolar transistors Tr1, Tr2, Tr3. Each hatched portion of the regions 16 identifies the bipolar transistors Tr1, Tr2, or Tr3 which are interconnected in a subsequent wiring step and put to practical use. In FIG. 4(a), ten (10) bipolar transistors Tr.sub.1 are used, and in FIGS. 4(b) and (c) ten (10) bipolar transistors Tr.sub.2 and Tr.sub.3 are similarly used, respectively.
As will be seen from FIGS. 4A to 4C, although in this example each of the three kinds of bipolar transistors Tr1, Tr2 and Tr3 are prepared in groups of 10s, only some of them are actually used, leaving the others unused.